This invention relates to trench-gate semiconductor devices, for example cellular power MOSFETs (insulated-gate field-effect transistors), and to their manufacture, wherein the gate comprises a metal silicide material.
Trench-gate semiconductor devices are known, comprising a gate trench that extends into a semiconductor body from a body surface, through a channel-accommodating region between a source region and an underlying drain region. The gate is capacitively coupled to the channel-accommodating region by an intermediate gate dielectric layer at a wall of the trench. U.S. Pat. No. 6,087,224 (our reference PHB34245) discloses an advantageous method of manufacturing such trench-gate semiconductor devices, using self-aligned masking techniques in a flexible device process with good reproducibility. In particular, narrow trench-gates can be formed, and the source region and a source contact window can be defined in a self-aligned manner with respect to this narrow trench. The whole contents of U.S. Pat. No. 6,087,224 are hereby incorporated herein as reference material.
The resistance of the trench-gate increases as its width is reduced. This becomes particularly important in large cellular layouts having a significant path length from a given cell to the gate metallisation. U.S. Pat. No. 6,087,224 discloses a wide variety of embodiments, including options on different gate materials. In its detailed examples the trench-gate is of doped polycrystalline silicon (commonly termed poly-Si), but U.S. Pat. No. 6,087,224 also discloses using other materials for the gate, such as a thin metal layer that forms a silicide with the poly-Si, or forming the whole gate of a metal instead of poly-Si.
Various approaches to the development of tungsten and tungsten silicide (WSix) as trench-gate materials are described in the ISPSD""2000 paper xe2x80x9cTungsten and Tungsten Silicide (WSix) as Gate Materials for Trench MOSFETsxe2x80x9d by Ambadi et al., pages 181 to 184 of the Proceedings of 12th International Symposium on Power Semiconductor Devices and ICs, Toulouse, May 22nd to 25th 2000. Although promising low gate resistance, it is recognised that these metal/silicide gates pose significant process development and integration challenges. The whole contents of this ISPSD""2000 paper are hereby incorporated herein as reference material.
Thus, deposition of the metal or silicide directly on the gate dielectric (usually oxide) is problematic in reducing the work function, and hence changing the threshold voltage of the device. Furthermore, contaminants such as fluorine can penetrate into the gate oxide from the deposited metal/silicide and can change the electrical properties of the gate oxide. Directly deposited silicides also suffer from poor adhesion to gate oxides. In attempting to avoid these problems, it is proposed in the ISPSD""2000 paper to deposit and/or grow different layer stacks within the gate trench, for example, a W layer on a barrier layer (Ti or TiN) on a very thin poly-Si layer on the gate oxide, and a W layer on a WSix layer on a thin poly-Si layer on the gate oxide. These approaches are quite complex and not easy to integrate with other process steps in the device manufacture. Particularly with very narrow trenches, voids can occur in the gate, for example due to imperfect in-fill of the trench by the deposited layer stack, and/or by silicon diffusion from the poly-Si to the tungsten.
It is an aim of the present invention to provide an alternative silicide-gate structure that is well suited to the inclusion of a substantial silicide part (for reducing gate resistance) while avoiding and/or reducing many of these disadvantages of previous silicide gate schemes.
According to a first aspect of the present invention, there is provided a trench-gate semiconductor device, wherein
the trench-gate comprises a part of semiconductor material adjacent to the gate dielectric layer adjacent to the channel-accommodating region of the device,
the gate protrudes upwardly from the trench in the form of a silicide upstanding part which is of a metal silicide material between its top and sidewalls above the level of the body surface, and
the gate dielectric layer at least adjacent to the channel-accommodating region is separated from the metal silicide material by at least the semiconductor part of the gate and by the protrusion of the silicide part upward above the level of the body surface.
The protrusion of the upstanding silicide part above the level of the body surface permits the inclusion of a substantial volume of silicide (to reduce gate resistance) without prejudicing other features such as: the quality of the gate dielectric adjacent to the channel-accommodating region; the device threshold voltage as determined by the semiconductor doping level of the lower gate part adjacent to this area of the gate dielectric; and good trench in-fill even with a very narrow trench. Generally, the protrusion of the silicide upstanding part of the gate above the level of the body surface may be larger than half the width of the trench. This protrusion may typically be as large as the width of the trench or larger, for example several times larger than the width of the trench.
Such a device structure in accordance with the invention is compatible with device manufacture using a variety of advantageous self-aligned processes, as described below.
According to a second aspect of the invention there is provided a manufacturing process that includes the following sequence of steps:
(a) providing at a surface of a semiconductor body a masking pattern having therein a window that is used for self-aligning a gate trench and parts of the gate formed in the subsequent steps (b) to (d);
(b) etching the trench into the semiconductor body within the window, and forming a dielectric layer at the walls of the trench for capacitively coupling the gate to the channel-accommodating region,
(c) depositing and then etching back semiconductor gate material to provide the semiconductor gate material on the dielectric layer in the trench without protruding above the masking pattern at the window, and
(d) then providing at the window a thickness of metal silicide material at the top of the semiconductor gate material sufficient to form a silicide upstanding gate part having a top and sidewalls that protrude upward above the level of the body surface.
The metal silicide material may be deposited on top of the semiconductor gate material in the trench, or it may be grown into the top and sidewalls of an upstanding part of the semiconductor gate material at the window. In either case, the gate dielectric layer (at least adjacent to the channel-accommodating region) is protected from the metal silicide by (at least a remaining part of) the semiconductor material of the gate and by the protrusion of its silicide part upward above the level of the body surface.
Sidewall extensions may be used to narrow the window where the silicide is provided, thereby laterally spacing the upstanding silicide part from the walls of the trench. Synergy with the advantageous method disclosed in U.S. Pat. No. 6,087,224 is possible. Thus, according to another aspect of the present invention, the said window of the masking pattern provided in step (a) may be a wide window that is then narrowed by providing sidewall extensions at the sidewalls of the wide window. The trench may be etched in step (b) at the narrower window, and the source region may be provided so as to be self-aligned with the trench-gate by means of the sidewall extensions. Depending on how the silicide is formed, these sidewall extensions may be retained or removed before providing the metal silicide in step (d). They and/or further sidewall extensions may be used in the definition of the silicide upstanding part of the gate.
According to a further aspect of the invention there is provided a manufacturing process that includes the following sequence of steps:
(a) providing at a surface of a semiconductor body a masking pattern comprising upper and lower layers through which a window extends at an area of the body where the trench-gate is to be provided,
(b) etching a trench for the gate into the body at the window, and forming a gate dielectric layer at the walls of the trench,
(c) providing silicon gate material in the trench and in the window, and then removing the upper layer of the masking pattern such that the silicon gate material has an upstanding upper part that protrudes above the adjacent surface of the lower layer of the masking pattern,
(d) depositing a silicide-forming metal over the silicon gate material and over the lower layer of the masking pattern, and heating at least the metal to grow a metal silicide into the silicon gate material from the top and side-walls of the upstanding upper part, and
(e) removing the un-silicided metal so as to leave a partially-silicided trench-gate protruding from the semiconductor body.
Both these aspects of the invention use a two-part masking pattern (either laterally as sidewall extensions at a wide window, or vertically as upper and lower layers). A two-part masking pattern of different materials can be particularly useful when the silicide material is provided by alloying a silicide-forming metal into an upstanding part of the semiconductor gate material in the window. Thus, the two-part masking pattern may be used when etching the trench and filling it with the semiconductor gate material to a level above the body surface. Thereafter one part of the two-part masking pattern may be removed (for example the sidewall extensions, and/or the upper layer), thereby creating a space for the silicide-forming metal to contact the sidewalls as well as the top of the upstanding part of the semiconductor gate material, and so to be alloyed therein.